This application claims the priority of Korean Patent Application No. 2003-28875, filed on May 7, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method for testing semiconductor devices, and more particularly, to a method for efficiently testing a remnant batch of semiconductor devices.
2. Description of the Related Art
Testers generally test the quality of semiconductor devices (referred to as semiconductor integrated circuits (ICs) and are automated devices that operate under the control of a programmed computer. The testers load the semiconductor devices to be tested into a test tray, transfer the semiconductor devices in the test tray to a test site, electrically test the semiconductor devices in the test tray at the test site, classify them into high and low quality semiconductor devices, and remove the classified semiconductor devices from the test site.
The testers also include a transfer unit (hereinafter referred to as a handler) that transfers the semiconductor devices to be tested. The handler transfers the semiconductor devices to the test site, electrically connects the semiconductor devices to a socket in a test head, and removes the tested semiconductor devices from the test site according to the quality of the semiconductor devices.
As semiconductor memory devices, such as dynamic random access memories (DRAMs), tend toward large capacity and multiple pins, the development of testers used for the semiconductor memory devices has put an emphasis on throughput. It takes considerable time to electrically test semiconductor devices that have large capacities. As a result, testing costs more. To solve this problem, testers for the semiconductor memory devices generally have use a parallel test method. The parallel test method tests a plurality of semiconductor devices simultaneously rather than each in sequence. At present, parallel test methods for simultaneously testing 64 or 128 semiconductor DRAMs are feasible.
In a conventional test method, 64 or 128 semiconductor devices to be tested are loaded into a test tray for a test. But devices that test as low quality are retested, even if only one such semiconductor device is loaded into a test tray. As a result, the testers operate at less than full capacity, and efficiency is impaired.